The present invention relates to a semiconductor memory test equipment which tests a semiconductor for correct write and read operations and, in case of a defect being detected, makes an analysis of the defect.
In semiconductor memory test equipment it is general practice to generate an address and write data from a pattern generator, access a memory under test by the address for writing therein the write data or reading out therefrom stored data, and compare the read-out data with expected value data, i.e. correct data, thereby testing the memory for correct write and read operations. Some of the semiconductor memory test equipment is arranged not only to decide whether the memory under test is non-defective or defective but also to make an analysis of a defect, such as the detection of the position and the cause of the defect, in the case of the memory being defective.
In the test of a semiconductor memory, there has been employed such a method that masks a particular bit of the memory test result from being provided, or that outputs the test result as a correct one regardless of the actual test result. Sometimes it is desired to test only a desired area of the memory under test as in the case where many defects exist in one area of the memory and only the other areas are tested, thus masking the area of many defects. In such a case, when selecting the test result of a desired area from the test results of all areas of the memory, a mistake may be made in the selection. Accordingly, if unnecessary areas are masked in advance, there is less possibility of making an error in the analysis of the test results. In the prior art, however, masking is performed by assigning the memory for each bit or address, so that in the case of masking a relatively wide area, the amount of data for masking, that is, what is called the mask data, increases. The mask data is stored in a mask memory which is read out by the same address as that for the memory under test, but when the amount of mask data is large, much time is required for transferring the mask data to the mask memory.
Accordingly, it will be very convenient if a particular block of the memory under test can be masked (block masking). In the case of such block masking, when one word is composed of a plurality of bits, a highly flexible masking operation can be performed for each bit of the word.
In the case where the memory under test is a read only memory, its expected value data is complex and difficult to obtain by a logic operation in many cases. To avoid this difficulty, it is customary in the art to prestore the expected value data as an expected value pattern in an expected value pattern memory and read it out by an address from a pattern generator to the memory under test to obtain the expected value data. To this end, the expected value data and the mask data are transferred to the expected value pattern memory and the mask memory respectively prior to the test. For the test of the memory, use is made of a complex test pattern so that defects may easily be found, and the same address is usually accessed a plurality of times in one test and the test pattern is long. As a consequence, the expected value pattern and the mask data pattern also become long, resulting in a relatively long time being required for the transfer. A semiconductor memory of a large storage capacity and high-speed operation has an operating cycle of, for example, about 20 nanoseconds, but the transfer of the expected value pattern or the mask data pattern from a central processor to the corresponding memory is approximately 1 microsecond per cycle, which is very slow in terms of the operation of a memory. Hence, the prior art method is disadvantageous in that the time for the transfer of the above data patterns is appreciably long as a whole.
Furthermore, for making an analysis of a defect, the memory under test is read out by an address from the pattern generator, and the read-out data is compared with the expected value data and then the comparison result is written in a defect address memory, using the same address as that for the memory under test. After the test, the defect address memory is read out and the data therefrom is inputted to the central processor for the defect analysis. Also in this case, however, since the operating cycle of the central processor is low in speed, much time is required especially when the memory under test has a large storage capacity.